The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Integrated circuit devices, such as transistors, are formed on semiconductor dies or chips. Integrated circuit features continue to scale in size to smaller dimensions. The shrinking dimensions of these features are challenging conventional techniques of forming features, such as through-silicon vias (TSVs), within a substrate.
Conventional vias are fabricated using chemical etching to produce a tunnel through the silicon or other substrate material. The hole is then filled with a conductive material to form a via. Conventional chemical etching techniques, if applied to the formation of relatively small TSVs, such as vias on the order of 10-20 μm in diameter, result in cone-shaped TSVs that have relatively large diameters at the top of the silicon surface, and relatively small diameters at the bottom of the silicon surface. As a result, the TSVs formed using conventional techniques cannot be situated close together, or close to other packaging or integrated circuit features, somewhat obviating the benefits of small-diameter TSVs.